This invention relates to a semiconductor device fabrication method and device design for suppressing hot carrier effects in MOS integrated circuits and more particularly to a technique for minimizing process-related aging effects in short gate-length MOSFET devices.
The problems of hot carriers, device aging and reliability have been recognized as one of the major constraints in device scaling The injection of hot carriers generated by impact ionization in the high drain field region of near-micrometer and submicrometer MOSFET devices degrades the device characteristics. The usual MOSFET processes and device structures, having a gate oxide layer in contact with the silicon substrate over the channel as shown in FIG. 1, are susceptible to hot-carrier trapping at the oxide-silicon interface. The trapped carriers accumulate over time and gradually lead to a shift in threshold voltage of the device that can amount to several tenths of volts or more. This means that circuit design aspects that are affected by gate threshold voltage are susceptible to change over the usual lifetime of circuit usage. In practice, it means that circuits designed with such devices to very close tolerances and initially operative are likely to fail after some period of time. A recent article by Chen et al. entitled "Suppression of Hot-Carrier Effects in Submicrometer CMOS Technology," IEEE Transactions on Electron Devices, Vol. 35, No. 12, Dec. 1988, pages 2210-2219, surveys state-of-the-art approaches to dealing with the problems of hot-carrier aging.
Hot-carrier aging was virtually nonexistent in circuits of MOSFET devices with a gate length of several micrometers. It becomes noticeable as gate lengths shorten to below 2 micrometers and becomes severe at gate lengths of one micrometer and below. Hot carrier generation is caused principally by ionization impact of drain current carriers with the silicon substrate lattice structure in a high electric field. As devices are scaled to smaller size while maintaining a constant drain voltage V.sub.D, the field strength increases. When field strength increases above about 10.sup.5 volt/cm., hot carriers unavoidably begin to be generated. One approach to managing hot carrier effects has been to reduce operating voltages for short gate integrated circuits. Commercial integrated circuit technology uses a standard 5 volts. Reductions to a range of 2.5-3 volts have been proposed to reduce the drain field in submicron circuit technologies. While providing some benefits, this approach leads to further problems of circuit compatibility, reduced performance, and reduced noise immunity. Ultimately, as devices continue to be scaled down, the high field problem returns.
Chen et al. discuss other approaches to controlling hot-carrier generation and injection, mostly involving positioning of current path and ionization region to minimize adverse effects. These approaches also are only stop-gap measures which will eventually fail as device sizes continue to be scaled down.
Processing aspects of hot-carrier aging are also considered by Chen et al. It is recognized as being desirable to reduce the number of hot-carrier trapping sites and that trapping at the oxide-silicon interface is the main cause of degradation. Countermeasures include forming and maintaining a high quality oxide layer and seeking to reduce Si--H bond breakage during hot-carrier injection. The latter approach proposes to reduce the hydrogen content of the device structure.
Hydrogen has long been used to fill dangling bonds, forming Si--H at the oxide-silicon interface to minimize the interface states. The Si--H bond can be easily broken by injected hot carriers, however, creating a trapped carrier at the site of the broken bond. It has been suggested to substitute fluorine for hydrogen, or to sinter the devices in a nitrogen atmosphere instead of hydrogen. Chen et al conclude, however, that it will become necessary to scale down operating voltage to 3.3 volts or below for submicrometer devices.
Another solution to the dangling bond problem was proposed by S. Iwamatsu in Japanese Pat Appln. (Kokai) No. 56-125,846, filed Mar. 7, 1980 and published Oct. 2, 1981. At that time, the state of the art in MOSFET technology used gate lengths of several micrometers. Hot carrier aging was not then a problem because hot carriers were not generated in the relatively long gate-length devices of that period. Iwamatsu addresses instead the problem of dangling bonds, explaining that the Si--SiO.sub.2 system has a constant electric charge due to unsaturated bonds at the interface. Because of the presence of interfacial level density Qss developed at the interface under the influence of this charge, it is difficult to set a low threshold voltage in MOSFET devices. Iwamatsu proposes to implant carbon into the silicon substrate through the gate oxide layer followed by heat treatment in a hydrogen atmosphere. So far as known by applicants, this technique has not been adopted commercially and appears to have given way to the conventional use of hydrogen alone, as discussed above, to saturate silicon bonding locations at the oxide silicon interface. This practice, however, as applied in the current state of the art, turns out to be one of the preconditions for hot-carrier trapping in short gate-length MOS devices.
Accordingly, a need remains for a better technique for suppressing hot-carrier aging in near-micrometer and submicrometer MOSFET devices and the like.